1. Field of the Invention
The invention relates to distributed processing systems. More particularly, the invention relates to a distributed processing system wherein discrete components communicate via a high level language such that functional systems may be rapidly developed and reduced to an ASIC implementation without the timing and electrical problems usually associated with ASIC development
2. State of the Art
Application Specific Integrated Circuits (ASICs) are widely used to implement sophisticated circuits for mass production. ASICs are developed in a number of different ways. One approach is to construct a prototype using discrete components wired together on a bread board or an etched circuit board, test and debug the prototype, and then migrate the circuit to an ASIC implementation. This approach has the advantage that the concept of the circuit is proven prior to ASIC implementation. A significant disadvantage of this approach is that the ASIC implementation utilizes very low level building blocks (e g., individual gates and registers) on a single chip which perform differently than the discrete components used in the prototype. The differences in performance of the on-chip components manifests itself in timing differences, parasitic capacitance, power balancing requirements, etc. Moreover, given the differences between the ASIC components and the prototype components, the mapping of the prototype to an ASIC chip may not be an optimal or even feasible implementation. Substantial redesign may be required during the migration to ASIC and the redesign introduces additional risk that the circuit will not perform as desired.
Another popular approach to ASIC design is to simulate a circuit using computer software which relies on a cell library supported by the ASIC manufacturer. Although this approach also involves careful attention to timing and the electrical characteristics of the final chip, there is greater confidence that the final chip will perform in the same manner as the simulated circuit. Nevertheless, software simulation is not always an accurate substitute for a real world prototype. The concept of the circuit is not tested in real world conditions until after the ASIC prototype is delivered, i.e. after a significant investment of time and money. Although the ASIC may perform according to the specifications of the software simulation, it may not be completely functional if the specifications are incorrect for a real world application. The development of an accurate specification for a real world circuit without any hardware testing is difficult and time consuming.
In most of the approaches to ASIC design and manufacture, once the circuit is reduced to an ASIC chip it cannot be easily and efficiently modified without redesigning a new chip. While there do exist field programmable gate arrays (FPGAs), these devices are too inefficient, because of their large die size, for higher volume applications.